SOLVING THE SYSTEM-LEVEL DESIGN RIDDLE

Editorial Webinar Series

Webinar: Solving the System-Level Design Riddle

Solving the System-Level Design Riddle Wednesday, December 10, 2014 at 1:00PM EST

In the last half of the 1990s EDA industry analysts began talking about the growing market for tools above the RTL handoff level. This new electronic systems level (ESL) tools market was supposedly going to explode and dramatically change the design landscape. Many companies were funded, but the market never really took off as forecasted. What happened?

The principle driving force for higher level tools, that is tools at a higher level of abstraction than gate-level RTL, was simply Moore’s Law. Every two years we were growing the transistor count of most devices by 1.5x to 2x. We would need to work more productively at a higher level of abstraction to get our designs completed on time with a reasonable number of engineers. What happened instead was the rapid development of the semiconductor intellectual property market (called SIP, or just IP).

Today, nearly all semiconductor design approaches use the Waterfall model. A Waterfall model is where one stage of design, like specification, is fully completed before the next stage of design begins. Parallel or concurrent engineering is barely used if at all. In an era where specifications change often and design cycles need to shrink far more, the Waterfall model is no longer of use to us.

On October 1, Sonics started an effort to organize like-minded engineers into a LinkedIn group aimed at getting a new methodology adopted. Modeled somewhat after the Agile Software revolution that started to effect the software industry in 2002, anyone can now join the LinkedIn group, “Agile IC Methodology.” Only three weeks after its launch, the group already had more than 200 members. Agile software techniques will not be able to completely map to a IC design methodology. Please join this group now and help us develop the next methodology for IC design.

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